Formation of device structures in semiconductor substrates such as silicon may include generating isolation structures such as shallow trench isolation (STI) structures, where oxide material may be deposited on pre-existing structures and etched to form a final isolation structure. In the case of fin-type field effect transistors (finFET), a series of sacrificial layers may be deposited on top of a monocrystalline semiconductor layer, such as silicon. The sacrificial layers may then be etched in a patterned etch to generate designed pattern structures including underlying monocrystalline semiconductor fins. This patterning may be followed by blanket deposition of an oxide layer on the patterned structures. The deposited oxide layer may subsequently be removed in part to form a final isolation structure that reveals at least a portion of underlying fins. Because the blanket deposition takes place over patterned structures, the removal of the deposited oxide may entail a series of operations, including chemical; mechanical polishing, to planarize the oxide layer as the final STI structure is being formed. While chemical mechanical polishing (CMP) processing may be an integral part of the formation of the final STI structure, the CMP processing may result in patterning effects, at the microscopic level, as well as at the macroscopic level across a substrate (wafer).
For example, in open regions, such as field oxide regions, where fin structures are sparse or absent, dishing of the oxide layer may take place during CMP processing, resulting in a non-uniform oxide layer thickness, especially in open regions. This non-uniformity may persist up to final etching operations where the semiconductor fins are revealed. With respect to these and other considerations the present disclosure is provided.